Reference timing signal apparatus and method
US7015762B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 19, 2004 |
| Grant date | Mar 21, 2006 |
| Priority date | — |
| Expiry date | Sep 10, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/14
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A reference timing signal apparatus with a phase-locked loop (PLL) has a computer algorithm which adaptively models the multiple frequencies of an oscillator following a training period. The oscillator is part of a PLL and the oscillation frequency thereof is controlled in response to the phase detector output. The computer algorithm processes the control signal applied to the oscillator. The computer algorithm updates the characteristics of the model relating to the aging and temperature of the oscillator, using for example, a Kalman filter as an adaptive filter, in accordance with a cumulative phase error in the PLL calculated during a given time interval. By the algorithm, the subsequent model predicts the future frequency state of the oscillator on which it was trained. The predicted frequency of the model functions as a reference to correct the frequency of the oscillator in the event that no input reference timing signal is available. Also, the calculated phase error is stored and is used while no input reference timing signal or accurate predicted frequency value is available. With the model updating algorithm, oscillators of low stability performance may be used as cellular…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.