Resonant clock distribution for very large scale integrated circuits
US7015765B2 · kind B2 · utility
23Cited by
1References
5Claims
0Family size
Assignee
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Key dates
| Filing date | Jul 26, 2004 |
| Grant date | Mar 21, 2006 |
| Priority date | — |
| Expiry date | Jul 26, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F1/10
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A circuit for distributing a clock signal in an integrated circuit includes a capacitive clock distribution circuit having at least conductor therein. At least one inductor is formed in a metal layer of the integrated circuit and is coupled to the clock distribution circuit. The inductor, generally in the form of a number of spiral inductors distributed throughout the integrated circuit, provides an inductance value selected to resonate with the capacitive clock distribution circuit. By operating the clock distribution circuit at resonance, power dissipation is reduced while skew and jitter performance can be improved.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.