Semiconductor memory apparatus
US7016247B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 29, 2004 |
| Grant date | Mar 21, 2006 |
| Priority date | — |
| Expiry date | Dec 29, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/785
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor memory apparatus including a simple circuit configuration and is capable of randomly accessing fuse data. A fuse cell 30 including a fuse 31 is connected to a pair of bit lines of a memory circuit. The fuse 31 and a fuse data output circuit (which includes a resistor 32 and an inverter 33) are connected to a pair of bit lines BLT and BLB of the memory circuit through a fuse selection switch 34. By allowing a column decoder 12 for selecting a pair of bit lines of the memory cell to also function as a decoder circuit for selecting a fuse, the bit lines of the memory circuit can be used as signal lines for outputting fuse data, whereby the circuit size is reduced and the circuit area is reduced.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.