Priority delay insertion circuit
US7016422B2 · kind B2 · utility
0Cited by
2References
24Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 9, 2001 |
| Grant date | Mar 21, 2006 |
| Priority date | — |
| Expiry date | Aug 26, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/00346
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A method of transmitting and prioritizing signals is disclosed. Higher priority signals are switched while lower priority signals are delayed until the higher priority signals have completed switching. The method is used in networks where coupling and capacitance effects are possible.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.