System and method for controlling a communication bus
US7016983B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 12, 2003 |
| Grant date | Mar 21, 2006 |
| Priority date | — |
| Expiry date | May 1, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/423
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for controlling communication. The method sends a first instruction from a first processor to a first device via a processor bus in electrical communication with a first bus, sends a control signal from the first processor to a selector, the selector switching electrical communication at least one signal line of the processor bus from the first bus to a second bus, sends a second instruction from the first processor to a second device, sends a control signal from the first processor to the selector, the selector switching electrical communication of the at least one signal line of the processor bus from the second bus to the first bus, and sends data from the first device to the first processor. In another aspect, the first processor may transmit the control signal to the selector after comparing a threshold value with a status signal indicating an amount of data stored in the buffer connected to the second processor, the status signal sent from the second processor to the first processor via a status bus.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.