Implementation of a content addressable memory using a RAM-cell structure
US7017005B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Aug 28, 2002 |
| Grant date | Mar 21, 2006 |
| Priority date | — |
| Expiry date | Jul 15, 2023 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S707/99952
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Method and device for arranging and storing data in a memory and for extracting the data from the memory in response to an input key, the method including the steps of: (a) providing at least a first array having at least two dimensions, the first array having rows and columns, the first array for storing a plurality of key entries; (b) providing at least a second array having at least two dimensions, the second array having rows and columns, the second array for storing a plurality of data entries, each of the data entries being associated with a particular one of the key entries; (c) arranging the key entries in monotonic order, and (d) identifying a single row among the rows of the first array as a sole row that may contain a particular stored key.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.