Mirrored tag snoop optimization
US7017054B2 · kind B2 · utility
8Cited by
10References
17Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jul 2, 2002 |
| Grant date | Mar 21, 2006 |
| Priority date | — |
| Expiry date | Nov 3, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F1/32
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and system for reducing snoop traffic on a processor bus coupling a cache memory and a processor. The processor is unable to perform a snoop operation while operating in a lower power state to conserve power. A copy of cache tag is maintained in a memory controller coupled to the processor bus. The memory controller performs snoop operations on the copy of the cache tag while the processor is placed in the lower power state. The processor exits the lower power state when an access to a modified cached line occurs.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.