Method and apparatus for fault-tolerance via dual thread crosschecking
US7017073B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 27, 2002 |
| Grant date | Mar 21, 2006 |
| Priority date | — |
| Expiry date | Feb 27, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/1695
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method (and structure) of concurrent fault crosschecking in a computer having a plurality of simultaneous multithreading (SMT) processors, each SMT processor simultaneously processing a plurality of threads, includes processing a first foreground thread and a first background thread on a first SMT processor and processing a second foreground thread and a second background thread on a second SMT processor. The first background thread executes a check on the second foreground thread and the second background thread executes a check on the first foreground thread, thereby achieving a crosschecking of the execution of the threads on the processors.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.