Sequential test pattern generation using clock-control design for testability structures
US7017096B2 · kind B2 · utility
8Cited by
11References
21Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 26, 2002 |
| Grant date | Mar 21, 2006 |
| Priority date | — |
| Expiry date | Jul 29, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/31704
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
Techniques for testing a sequential circuit comprising a plurality of flip-flops or other types of registers. The circuit is first configured such that substantially all feedback loops associated with the registers, other than one or more self-loops each associated with a corresponding one of the registers, are broken. Test patterns are then generated for application to the circuit. The test patterns are applied to the circuit in conjunction with partitioned clock signals each of which is associated with a corresponding level of the circuit containing at least one of the self-loops.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.