Variable mask field exposure
US7018753B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 5, 2003 |
| Grant date | Mar 28, 2006 |
| Priority date | — |
| Expiry date | Jan 30, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG03F7/70466
- WIPO fieldOptics
- WIPO sectorInstruments
Abstract
A method of fabricating integrated circuits according to a first design by imaging a first layer on a substrate using a first mask having a block of first patterns in common with a second design, but without any other patterns of the first or second designs and imaging a second layer on the substrate using a second mask having a block of second patterns unique to the first design and at least one third layer pattern. The block of first patterns is repeatedly exposed in a first grid and the block of second patterns is repeatedly exposed in a second grid, each without overlap in the corresponding layer. The grids are aligned such that the integrated circuits and test structures in scribe lines between the integrated circuits are properly formed on the substrate. The first patterns can be for large fields and the second patterns can be for small fields.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.