Single polisilicon emitter bipolar junction transistor processing technique using cumulative photo resist application and patterning
US7018778B1 · kind B1 · utility
6Cited by
6References
6Claims
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Key dates
| Filing date | Mar 24, 2003 |
| Grant date | Mar 28, 2006 |
| Priority date | — |
| Expiry date | Aug 26, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D10/861
Abstract
A process for forming a bipolar transistor where the doping implantation of the extrinsic base regions does not affect the emitter doping levels. The techniques is to not remove the photoresist layer used to define the poly emitter contact. The photoresist layer for defining the extrinsic base regions overlays the photoresist layer over the emitter poly. When the base photoresist is processed to expose the base regions the photoresist over the emitter poly remains in tact. In this arrangement the base implantation is prevented from driving through the emitter poly and affecting the doping levels in the emitter.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.