Method of manufacturing integrated semiconductor devices and related devices
US7018861B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 24, 2003 |
| Grant date | Mar 28, 2006 |
| Priority date | — |
| Expiry date | Apr 26, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01S2304/04
- WIPO fieldOptics
- WIPO sectorInstruments
Abstract
Integrated semiconductor devices are manufactured by providing a layered semiconductor structure having an exposed surface and providing a mask on the exposed surface thereby defining a masked region in the layered structure underneath said mask. The mask has a main direction of extension with a width across the main direction and an end portion. The layered structure is etched over a given depth starting from the exposed surface, whereby the masked region is left substantially unaffected by the etching process and has an end surface extending underneath the end portion of the mask. A further layered semiconductor structure is grown around the masked region to produce an integrated layered semiconductor structure having at the end surface an interface between the layered structure and the further grown structure. The mask width is selected to be less than 50 microns.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.