Double-gated transistor circuit
US7019342B2 · kind B2 · utility
45Cited by
25References
12Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 21, 2003 |
| Grant date | Mar 28, 2006 |
| Priority date | — |
| Expiry date | Dec 25, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D86/201
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An OR gate circuit includes double-gated four terminal transistor with independent gate control. First and second inputs are independently coupled to the top and bottom gates of the transistor. The drain is coupled to an output and precharged to a low voltage. An input to either the top or bottom gates results in a high voltage to the drain and an output value of 1.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.