Split computer architecture
US7020732B2 · kind B2 · utility
8Cited by
28References
16Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 6, 2003 |
| Grant date | Mar 28, 2006 |
| Priority date | — |
| Expiry date | Mar 6, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L69/329
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A network interface is described in which a single computer bus is split over a long distance into two or more inter-communicating buses. On one bus, processing and applications are provided and on the other remote bus, peripheral and local controllers are provided. The buses communicate through a series of: bridge, FPGA, FPGA and bridge. Between the FPGAs, a communication path provides long distance communication.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.