Providing an arrangement of memory devices to enable high-speed data access
US7020757B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 27, 2003 |
| Grant date | Mar 28, 2006 |
| Priority date | — |
| Expiry date | Mar 2, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/4096
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory subsystem includes multiple memory modules coupled by point-to-point links. A memory controller is coupled by a point-to-point link to a first memory module, which is turn is coupled by another point-to-point link to another memory module. Further memory modules may be coupled by respective point-to-point links in the memory subsystem. In some arrangements, each memory module tracks commands issued to other memory modules, such as more upstream memory modules. Also, in one example implementation, a clock is embedded within a data stream transmitted over a point-to-point link, so that an external clock is not employed in this example implementation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.