Techniques for reducing the rate of instruction issuance
US7020767B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 23, 2001 |
| Grant date | Mar 28, 2006 |
| Priority date | — |
| Expiry date | Feb 27, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/542
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and system in a multithreaded processor for processing events without interrupt notifications. In one aspect of the present invention, an operating system creates a thread to execute on a stream of the processor. During execution of the thread, the thread executes a loop that determines whether an event has occurred and, in response to determining whether an event has occurred, assigns a different thread to process the event so that multiple events can be processed in parallel and so that interrupts are not needed to signal that the event has occurred. Another aspect of the present invention provides a method and system for processing asynchronously occurring events without interrupt notifications. To achieve this processing, a first thread is executed to generate a notification that the event has occurred upon receipt of the asynchronously occurring event. A second thread is also executed that loops determining whether a notification has been generated and, in response to determining that a notification has been generated, performing the processing necessary for the event.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.