System and methods for fault path testing through automated error injection
US7020803B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 11, 2002 |
| Grant date | Mar 28, 2006 |
| Priority date | — |
| Expiry date | Apr 11, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/2215
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The system and methods described herein relate to testing and verifying the fault tolerance in fault tolerant systems. Fault logic integrated into a fault tolerant system permits automated testing of fault paths in system firmware and hardware dedicated to handling fault scenarios. Advantages of the disclosed system and methods include the ability to inject errors without the need to modify system firmware or hardware. Errors can be injected in a controlled manner and asynchronously to normal system firmware execution which permits improved coverage of firmware error paths. The automated error injection capability disclosed is applicable in both the development and production of fault tolerant systems.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.