Intra-decoder component block messaging
US7020826B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 23, 2002 |
| Grant date | Mar 28, 2006 |
| Priority date | — |
| Expiry date | Jun 18, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M13/1555
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A decoder and decoding method are described, in which a syndrome is calculated from a codeword in a syndrome generator, an error polynomial is generated based upon the syndrome in an error polynomial generator, an error location is determined from the error polynomial in the error location generator, an error magnitude is calculated from the error polynomial in the error magnitude generator and the codeword is corrected by a error corrected codeword generator responsive to location and error magnitude. An intra-decoder block messaging scheme is described in which one or more components generate inactivity messages to signal an ability to process data corresponding to a next codeword. A dual Chien search block implementation is described in which Chien block is used to determine the number of errors corresponding to a specified codeword, separately from error location and magnitude calculations performed by the Chien/Forney block. An enhanced Chien search cell architecture is described which utilizes an additional Galois field adder to synchronize the codeword and error vector, thereby decreasing delay and expense corresponding to an error correcting block implemented with a LIFO re…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.