Digital circuit layout techniques using identification of input equivalence
US7020855B2 · kind B2 · utility
7Cited by
12References
4Claims
0Family size
Inventor
Key dates
| Filing date | Aug 16, 2002 |
| Grant date | Mar 28, 2006 |
| Priority date | — |
| Expiry date | Jul 6, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/39
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A technique for analyzing digital circuits to identify pin swaps is provided for circuit layout and similar tasks in which the circuit is first decomposed into regions. Logic functions of the regions are decomposed into a directed graph of the logic functions. A swap structure is created in accordance with the directed graph to facilitate identification of input equivalences.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.