Stably-biased cascode networks
US7023281B1 · kind B1 · utility
7Cited by
10References
32Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Jul 23, 2004 |
| Grant date | Apr 4, 2006 |
| Priority date | — |
| Expiry date | Nov 17, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03F1/30
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Cascode bias structures are provided which enhance control of cascode biases over disturbing effects such as temperature and process variations. Because this enhanced control stabilizes the biases over these disturbing effects, the biases can be reduced to thereby expand the cascode's dynamic range and yet assure that the cascode transistors continue to operate in their proper transistor regions.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.