Coarse tuning for fractional-N synthesizers having reduced period comparison error
US7023282B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 29, 2004 |
| Grant date | Apr 4, 2006 |
| Priority date | — |
| Expiry date | Aug 23, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03J2200/10
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An improved coarse tuning process for fractional-N frequency synthesizers is provided. In general, a coarse tuning circuit controls a phase lock loop (PLL) of a frequency synthesizer. During coarse tuning, a reference signal used to control an output frequency of the PLL is provided to the coarse tuning circuitry and is divided by a factor M to provide a divided reference signal. A controllable oscillator (CO) output signal from a CO in the PLL is divided by an N divider in the PLL to provide a divided CO signal. The periods or, equivalently, frequencies of the divided CO signal and the divided reference signal are compared, and the result is used to select an appropriate tuning curve for the CO. In order to reduce a period comparison error, synchronization circuitry operates to synchronize the N divider of the PLL and an M divider of the coarse tuning circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.