Method and apparatus for segmented, switched analog/digital converter
US7023372B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 9, 2005 |
| Grant date | Apr 4, 2006 |
| Priority date | — |
| Expiry date | Feb 9, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M1/806
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A switched-capacitor circuit for use in analog-to-digital conversion samples an input signal with respect to a reference voltage such that it significantly reduces a DAC settling time interval during each bit trial. In one exemplary embodiment, the switched-capacitor circuit having first and second groups of capacitor banks is coupled to a first input of a comparator and to a control circuit which provides control signals such that during a switching sequence, an equal value of capacitance is selected from each of the first and second groups of capacitor banks to reduce the DAC settling time interval, thereby improving the conversion rate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.