Method and apparatus for digital data synchronization
US7023942B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 9, 2001 |
| Grant date | Apr 4, 2006 |
| Priority date | — |
| Expiry date | Mar 3, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04J2203/0089
- WIPO fieldTelecommunications
- WIPO sectorElectrical engineering
Abstract
Synchronization and desynchronization of a data signal transported in a synchronous frame across a synchronous communications network, such as SONET/SDH, reduces waiting-time jitter. A timing estimate (F) indicative of a relationship between a data rate (f1) of the data signal and a reference frequency (f2) of the synchronous communications network is calculated and communicated through the synchronous communications network, for example in the Synchronous Payload Envelope of a SONET frame. The data signal is recovered using a desynchronizer Phase-Locked Loop steered by the timing estimate (F). The timing estimate (F) can be any one or more of: a ratio between the data rate (f1) and the reference frequency (f2); a difference between the data rate (f1) and the reference frequency (f2); and a phase difference between a recovered data clock signal associated with the data rate (f1) and a reference clock signal associated with the reference frequency (f2).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.