Method and apparatus for jitter reduction in phase locked loops
US7023945B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 17, 2002 |
| Grant date | Apr 4, 2006 |
| Priority date | — |
| Expiry date | Mar 10, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/095
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A method and apparatus for jitter reduction in a Phase Locked Loop (PLL) that includes determining a size of a original charge pump adequate to generate an appropriate control voltage to a Voltage Controlled Oscillator (VCO) of a PLL based on the charge pump receiving a single up signal or down signal within one cycle of a PLL input reference clock. N number of the up signal or down signal are generated to a second charge pump 1/N the size of the original charge pump. The N number of the up signal or the down signal occurs within one cycle of the PLL input reference clock. The second charge pump generates N second control voltage corrections each being 1/N the amplitude of the appropriate control voltage glitch, thus minimizing glitches on the second control voltages and reducing jitter to the VCO.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.