Delay element calibration
US7024324B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 27, 2004 |
| Grant date | Apr 4, 2006 |
| Priority date | — |
| Expiry date | Jun 20, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R29/0273
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A method for calibrating a delay element is described herein. In some embodiments, the method may include generating a clock signal with a clock edge, generating a reference signal with a reference edge using an adjustable delay line to delay the clock signal, and delaying a selected one of the clock signal and the reference signal through an array delay line having an array delay element with an array delay. In some embodiments, the method may further include adjusting the adjustable delay line to obtain a first adjustable delay so that the clock and reference edges are aligned on one side of the array delay element, adjusting the adjustable delay line to obtain a second adjustable delay so that the clock and reference edges are aligned on the other side of the array delay element, and ascertaining a delay difference between the first and the second adjustable delays to determine a value of the array delay provided by the array delay element. Other embodiments of the present invention may include, but are not limited to, apparatuses and systems adapted to facilitate practice of the above-described method.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.