Processing apparatus
US7024442B2 · kind B2 · utility
4Cited by
7References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 20, 2001 |
| Grant date | Apr 4, 2006 |
| Priority date | — |
| Expiry date | Jun 12, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F17/142
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A processing apparatus includes a memory capable of storing data, a butterfly arithmetic unit for performing butterfly computation processes, and a bit-reversed order shuffle processing unit for writing results obtained by butterfly computation processes performed by the butterfly arithmetic unit at addresses in the memory after bit-reversed order shuffle instead of writing the results at addresses in the memory in processing order. The data written by the bit-reversed order shuffle processing unit are discrete fast Fourier transform results.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.