DC offset self-calibration system for a switching amplifier
US7026866B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Mar 23, 2004 |
| Grant date | Apr 11, 2006 |
| Priority date | — |
| Expiry date | Jun 24, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03F3/2173
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Techniques for DC offset cancellation are described. According to one embodiment, an amplifier has at least one output and first and second supply rails. The amplifier includes offset cancellation logic which is operable in a calibration mode to generate a first offset cancellation signal when the at least one output is coupled to a first voltage corresponding to the first supply rail, and a second offset cancellation signal when the at least one output is coupled to a second voltage corresponding to the second supply rail. The offset cancellation logic is further operable to facilitate at least partial cancellation of an offset voltage associated with the at least one output during a normal operation mode using a third offset cancellation signal which substantially corresponds to an average of the first and second offset cancellation signals.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.