Real time binary arithmetic encoding
US7026961B2 · kind B2 · utility
2Cited by
3References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 3, 2004 |
| Grant date | Apr 11, 2006 |
| Priority date | — |
| Expiry date | Jun 5, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M7/4006
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An apparatus comprising a first circuit and a second circuit. The first circuit may be configured to generate a plurality of signals in response to one or more of a context index and a binary symbol. The second circuit may be configured to generate a series of output bits in response to the plurality of signals. The memory may be configured to transfer the plurality of signals between the first circuit and the second circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.