Analog-to-digital converter and method with switched capacitors for reduced memory effect
US7026968B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Nov 2, 2004 |
| Grant date | Apr 11, 2006 |
| Priority date | — |
| Expiry date | Nov 19, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M1/167
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Methods and structures are provided that reduce conversion errors in pipelined analog-to-digital converters which are induced in one converter cycle by component memory of signals in one or more preceding converter cycles. The methods and structures include the use of digital filters that provide a digital representation of the residue of a preceding converter cycle, multiply this representation by an appropriate memory parameter, and sum the product with the digital representation of the residue of a current converter cycle to thereby reduce the memory effect. The methods and structures also form capacitors of switched-capacitor converter structures with sub-capacitors that are reconfigured (e.g., reversed or alternated between differential sides of differential amplifiers) in different converter cycles.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.