Shift register unit and signal driving circuit using the same
US7027550B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Aug 12, 2004 |
| Grant date | Apr 11, 2006 |
| Priority date | — |
| Expiry date | Sep 18, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C19/28
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A shift register unit. The shift register unit outputs a shift register signal according to a clock signal, an inverse clock signal and a start signal. The shift register has first and second clock inversion circuits, and an inverter. In the first clock inversion circuit, a third PMOS transistor has a third source coupled to the first voltage, a third gate and a third drain. A fourth PMOS transistor has a fourth source coupled to the third drain, a fourth gate and a fourth drain coupled to the second voltage. A fifth PMOS transistor has a fifth source coupled to the third drain, a fifth drain coupled to the first gate, and a fifth gate. A sixth PMOS transistor having a sixth source coupled to the third gate, a sixth drain coupled to the second gate, and a sixth gate coupled to the fifth gate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.