Single-ended loop test circuitry in a central office DSL modem
US7027589B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 27, 2002 |
| Grant date | Apr 11, 2006 |
| Priority date | — |
| Expiry date | Aug 20, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04M3/305
- WIPO fieldTelecommunications
- WIPO sectorElectrical engineering
Abstract
A central office modem (50) that includes the capability of single-ended loop testing (SELT) is disclosed. The modem (50) includes a digital signal processor (54), a codec (56), line driver and receiver circuitry (58), and a hybrid circuit (60), by way of which a subscriber loop (LOOP) can be driven and sensed. The line driver and receiver circuitry (58) may include a transformer (74a, 74b) for driving the loop (LOOP), or the output may be capacitively coupled. The line driver and receiver circuitry (58) includes active termination, by way of operational amplifiers (80a, 80b). Switches (82a, 82b; 84a, 84b) are provided to selectively enable and disable the active termination function, and to selectively bypass or include the hybrid circuit (60). This control of the line driver and receiver circuitry (58) provides the ability to calibrate out its own characteristics, providing high precision SELT measurements of the load impedance type, and of frequency domain reflectometry, and time domain reflectometry. A third set of switches (86a, 86b) selectively bypass receive path filter circuitry (78), to permit upstream and downstream noise measurements.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.