System and method for reducing access latency to shared program memory
US7028142B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Mar 25, 2003 |
| Grant date | Apr 11, 2006 |
| Priority date | — |
| Expiry date | Aug 4, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3814
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
System and method for reducing access latency to a shared program memory. The program memory is shared by more than one processor. The system includes fetch buffers (one per processor), prefetch buffers (one per processor), program fetch logic units (one per processor), and an arbiter. Each fetch buffer stores local instructions that are local to an instruction being used by an associated processor. Each prefetch buffer stores subsequent instructions that are subsequent to the local instructions stored in an associated fetch buffer. Each program fetch logic unit determines from where to fetch a next instruction required by the associated processor. The arbiter arbitrates between instruction fetch requests received for the fetch buffers and the prefetch buffers from the various processors. The arbiter determines which of the instruction fetch requests will next gain access to the program memory. Such a system improves latency by assigning a higher priority to fetch requests over prefetch requests or data requests.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.