Error correction code circuit with reduced hardware complexity
US7028247B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Dec 25, 2002 |
| Grant date | Apr 11, 2006 |
| Priority date | — |
| Expiry date | Sep 20, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M13/158
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An error correction code circuit with reduced hardware complexity is positioned inside a microprocessor. The microprocessor has a Galois field multiplier for performing a Galois field multiplication on data processed by the error correction code circuit. The error correction code circuit has a first register for storing an input data, a plurality of calculation units, a third register for storing an output data corresponding to the input data, and a controller for controlling operation of the error correction code circuit. Each calculation unit has a Galois field adder, and a second register electrically connected to the Galois field adder. The controller transmits data of each calculation unit to the same Galois field multiplier for a corresponding Galois field multiplication, and the result outputted by the Galois field multiplier is transmitted back to the error correction code circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.