IC layout buffer insertion method
US7028280B1 · kind B1 · utility
6Cited by
4References
24Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 26, 2002 |
| Grant date | Apr 11, 2006 |
| Priority date | — |
| Expiry date | Mar 14, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/39
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An integrated circuit (IC) layout system designs nets for interconnecting cells forming modules of a hierarchical IC design. Each module is defined as having one or more ports through which the nets extend when linking cells forming different modules. The layout system automatically inserts buffers into selected segments of the nets to reduce signal path delays through the nets and assigns the inserted buffers to selected modules. However the layout system inserts buffers only into those net segments for which a buffer insertion would not alter the number of ports any module needs to accommodate the net.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.