Patent · US Expired

Planarization with reduced dishing

US7029591B2 · kind B2 · utility

2Cited by

8References

1Claims

0Family size

Assignee

LSI Logic Corporation · US

Inventors

Wilbur G. Catabay · Saratoga, US
Wei-Jen Hsia · Sunnyvale, US
Hao Cui · Gresham, US

Key dates

Filing date	Apr 23, 2003
Grant date	Apr 18, 2006
Priority date	—
Expiry date	Sep 16, 2023

Classification

Technology area (CPC H)Electricity
CPC primaryH01L21/7684
WIPO fieldSemiconductors
WIPO sectorElectrical engineering

Abstract

A method of forming a planarized layer on a substrate, where the substrate is cleaned, and the layer is formed having a surface with high portions and low portions. A resistive mask is formed over the low portions of the layer, but not over the high portions of the layer. The surface of the layer is etched, where the high portions of the layer are exposed to the etch, but the low portions of the layer underlying the resistive mask are not exposed to the etch. The etch of the surface of the layer is continued until the high portions of the layer are at substantially the same level as the low portions of the layer, thereby providing an initial planarization of the surface of the layer. The resistive mask is removed from the surface of the layer, and all of the surface of the layer is planarized to provide a planarized layer.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.