Dual-gate structure and method of fabricating integrated circuits having dual-gate structures
US7030024B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 23, 2002 |
| Grant date | Apr 18, 2006 |
| Priority date | — |
| Expiry date | Jun 9, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/0144
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of fabricating a dual-gate on a substrate and an integrated circuit having a dual-gate structure are provided. A first high-K dielectric layer is formed in a first area defined for a first gate structure and in a second area defined for a second gate structure. A second high-K dielectric layer is formed in the first and second areas. The first high-K dielectric layer has a lower etch rate to an etchant relative to the second high-K dielectric layer. The second high-K dielectric layer is etched from the second area to said first high-K dielectric layer with the etchant, and a gate conductive layer is formed in the first and second areas over the second high-K dielectric layer and first high-K dielectric layer, respectively.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.