Electronic assembly with stacked integrated circuit die
US7030317B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Apr 13, 2005 |
| Grant date | Apr 18, 2006 |
| Priority date | — |
| Expiry date | Aug 1, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/3011
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An electronic assembly with a plurality of stacked integrated circuit (IC) die includes a base substrate, a first IC die, a second IC die, a signal routing first interconnect and a signal routing second interconnect. The first interconnect is partially positioned between the first and second IC dies. The second interconnect is partially positioned adjacent the first side of the second IC die. The first interconnect couples a first contact of the first IC die to a first trace of the base substrate and a second contact of the second IC die to a second trace of the base substrate. The first and second interconnects, in combination, couple the first contact of the second IC die to the first trace.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.