Semiconductor package having built-in micro electric mechanical system and manufacturing method thereof
US7030494B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jun 22, 2004 |
| Grant date | Apr 18, 2006 |
| Priority date | — |
| Expiry date | Jun 22, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/19041
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor package includes a semiconductor structure having a plurality of electrodes for external connection which are provided on a semiconductor substrate, an insulation layer provided on the semiconductor structure, an upper wiring having connection pad portions and provided on the insulation layer such that at least parts of the upper wiring are connected to the electrodes for external connection of the semiconductor structure, a micro electric mechanical system electrically connected to parts of the connection pad portions of the upper wiring, pole electrodes provided so as to be electrically connected to other connection pad portions of the upper wiring, and an upper insulation film covering the vicinities of the pole electrodes and at least the vicinity of the micro electric mechanical system.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.