Frequency compensation scheme for low drop out voltage regulators using adaptive bias
US7030677B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Nov 12, 2003 |
| Grant date | Apr 18, 2006 |
| Priority date | — |
| Expiry date | Feb 9, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG05F1/575
- WIPO fieldControl
- WIPO sectorInstruments
Abstract
A method and circuits to improve the stability of low dropout voltage regulators having an adaptive biased driving stage. Said improvement of stabilization is valid through the total range of output current possible. A serial impedance is added to the gate capacitance of the PMOS pass device of said LDO. Said serial impedance could be a resistor or a transistor. In case of low load currents said impedance is not dominating, for high load currents said impedance keeps the gate pole close to the resonance frequency of the output tank. In case of medium load currents, wherein the inner resistance of the driving stage is about equal to said serial impedance, the gate pole could get too low. This problem is solved by reducing said serial impedance by shunting. Said shunting can be performed stepwise depending on the size of the load current. A special circuitry detects the condition of medium load currents and can initialize the shunting of said serial impedance accordingly in order to keep the gate pole on the optimum frequency.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.