Suppressing digital-to-analog converter (DAC) error
US7030792B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Sep 28, 2005 |
| Grant date | Apr 18, 2006 |
| Priority date | — |
| Expiry date | Sep 28, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M3/464
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A digital-to-analog converter (DAC) error suppression arrangement suppresses DAC error arising from mismatched elements contained in a DAC (640 and/or 645) that is part of a modulator (FIG. 6). A low pass averaging (LPA) index decoder 650 controls a shifting arrangement 635 to shift a digital word T2 derived from modulator output Y so that the DAC error distribution constitutes a low pass profile (FIG. 5). Thus, DAC error is suppressed at higher frequencies (close to half the sampling rate), thereby providing improved spurious free dynamic range (SFDR). The LPA index decoder 650 causes the shifting arrangement 635 to shift the digital word T2 using only a single pointer per clock cycle.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.