Low power register apparatus having a two-way gating structure and method thereof
US7031204B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 15, 2004 |
| Grant date | Apr 18, 2006 |
| Priority date | — |
| Expiry date | Jul 28, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/1078
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A register apparatus and method for providing a two-way gating structure for receiving a write enable signal, a chip select signal, at least one read signal, and an address signal for a register. The apparatus and method comprise a two-way gating portion for generating a coded write address by AND-operating a first signal with the address signal, a coded read address by AND-operating a second signal with the address signal, and a reader activation signal by AND-operating the read signal with the second signal. The first and second signals are generated by AND-operating the chip select signal with the write enable signal and by AND-operating the chip select signal with an inverted write enable signal. A writer decodes the coded write address and generates write signals using the decoded write address and data received from a bus. A reader decodes the coded read address and generates data using data read from the register and the decoded read address.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.