Receiver and low power digital filter therefor
US7031377B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 26, 2001 |
| Grant date | Apr 18, 2006 |
| Priority date | — |
| Expiry date | Jan 30, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03H17/0254
- WIPO fieldTelecommunications
- WIPO sectorElectrical engineering
Abstract
A digital filter or a receiver including a digital filter having at least two multiple stage shift registers. A plurality of multipliers corresponding in number to the number of stages in the at least two multiple stage shift registers receive as a first input an output from a corresponding stage of the at least two multiple stage shift registers. A tap weight shifter is coupled to a tap weight source to receive tap weights. The tap weight shifter is coupled to provide a second input to each multiplier. Each multiplier produces an output that is the product of inputs thereto. An adder sums the multiplier outputs to provide a sum output. The tap weight shifter then circularly shifts the tap weights and another multiply-add operation occurs. Several shift/multiply/add cycles may occur before data is again shifted into the at least two multiple stage shift registers, and another multiply-add operation occurs.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.