Prefetching data in a computer system
US7032076B2 · kind B2 · utility
10Cited by
13References
19Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 16, 2002 |
| Grant date | Apr 18, 2006 |
| Priority date | — |
| Expiry date | May 17, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0862
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and apparatus to detect and filter out redundant cache line addresses in a prefetch input queue, and to adjust the detector window size dynamically according to the number of detector entries in the queue for the cache-to-memory controller bus. Detectors correspond to cache line addresses that may represent cache misses in various levels of cache memory.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.