Configurable hardware register stack for CPU architectures
US7032104B1 · kind B1 · utility
2Cited by
7References
18Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Dec 15, 2000 |
| Grant date | Apr 18, 2006 |
| Priority date | — |
| Expiry date | Jan 7, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/30134
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A circuit comprising a register stack and a control circuit. The register stack may be configured as (i) a plurality of segments addressable through a segment address signal and (ii) a plurality of registers within each of the plurality of segments. The plurality of registers are generally addressable through a register address signal. The control circuit may be configured to (i) store a plurality of register states, (ii) store a segment count signal, and (iii) present the segment address signal responsive to the plurality of register states, the segment count signal, and the register address signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.