Bit error rate tester
US7032139B1 · kind B1 · utility
38Cited by
4References
39Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 24, 2002 |
| Grant date | Apr 18, 2006 |
| Priority date | — |
| Expiry date | Feb 8, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L1/203
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
The present invention is a bit error rate tester that may operate on network paths having devices that add or drop idles within a transmitted bit sequence. In particular, the bit sequence determines whether a received bit sequence is synchronized. If the received sequence is not synchronized or if a certain event/threshold is reached, then the bit error rate tester re-synchronizes the sequence prior to analysis. Also, the bit error rate detector is able to operate on high-speed networks and provide bit granularity measurements.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.