Memory circuit having parity cell array
US7032142B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 17, 2002 |
| Grant date | Apr 18, 2006 |
| Priority date | — |
| Expiry date | Dec 27, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2211/4062
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory circuit has: a real cell array; a parity generating circuit for generating a parity bit from data of the real cell array; a parity cell array; a refresh control circuit, which sequentially refreshes the real cell array, and when an internal refresh request and a read request coincide, prioritizes a refresh operation; a data recovery section, which, in accordance with the parity bit read out from the parity cell array, recovers data read out from the real cell array; and an output circuit for outputting data from the real cell array. Further, the memory circuit has a test control circuit, which, at a first test mode, prohibits a refresh operation for the real cell array to output data read out from the real cell array, and, at a second test mode, controls the output circuit so as to output data read out from the parity cell array.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.