ACS unit in a decoder
US7032165B2 · kind B2 · utility
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3References
21Claims
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Key dates
| Filing date | Feb 4, 2003 |
| Grant date | Apr 18, 2006 |
| Priority date | — |
| Expiry date | Jul 21, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M13/4107
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A device for implementing a function of add-compare-select type in an error correction code decoder, having first and second adders for adding, respectively for first and second branches, branch metric values, intermediate value of former state metrics, and values of former state metric offset, thus forming first and second values of present state metrics; a comparator, coupled to the first and second adders, for selecting the highest value from among the first and second values; circuitry for determining a digital value of present state metric offset including a single bit, based on the first and second values.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.