Method of fabricating a MOS transistor with elevated source/drain structure using a selective epitaxial growth process
US7033895B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 13, 2004 |
| Grant date | Apr 25, 2006 |
| Priority date | — |
| Expiry date | May 9, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/0212
Abstract
In a metal-oxide semiconductor (MOS) transistor with an elevated source/drain structure and in a method of fabricating the MOS transistor with the elevated source/drain structure using a selective epitaxy growth (SEG) process, a source/drain extension junction is formed after an epi-layer is formed, thereby preventing degradation of the source/drain junction region. In addition, the source/drain extension junction is partially overlapped by a lower portion of the gate layer, since two gate spacers are formed and two elevated source/drain layers are formed in accordance with the SEG process. This mitigates the short channel effect and reduces sheet resistance in the source/drain layers and the gate layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.