Method and circuit for increased noise immunity for clocking signals in high speed digital systems
US7034566B2 · kind B2 · utility
3Cited by
8References
15Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Feb 12, 2004 |
| Grant date | Apr 25, 2006 |
| Priority date | — |
| Expiry date | Feb 25, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/0005
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Aspects for increased noise immunity for clocking signals in high speed digital systems are described. The aspects include buffering a differential clock signal with a single buffer circuit for a plurality of load circuits and configuring the single buffer circuit to adjust to alterations in the number of load circuits receiving the differential clock signal. The configuring achieves a constant bandwidth and voltage level for the clock signal output while adjusting to alterations in the number of load circuits.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.