Pulsed dynamic keeper gating
US7034576B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 27, 2003 |
| Grant date | Apr 25, 2006 |
| Priority date | — |
| Expiry date | Jun 27, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/0963
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A circuit has been developed that reduces the effective strength of a keeper circuit during an interval in which at least one path of an evaluation circuit is sensitive to a keeper device. The keeper circuit includes a keeper gating device coupled to a keeper device that is responsive to a keeper control. The keeper device is sized to overcome leakage current in the evaluation circuit. In some configurations, the keeper circuit includes a weak keeper device that is minimally sized to overcome noise while the keeper device is effectively disabled. In some configurations, the reduction in effective strength of the keeper circuit occurs before arrival of the fastest signal coupled to a sensitive output path of the evaluation circuit and the effective strength is restored after arrival of the slowest signal coupled to the sensitive output path of the evaluation circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.